At this week’s IEEE IEDM 2018 conference, imec, the Leuven-based research and innovation hub has presented a first demonstration of 3D stacked FinFETs on 300mm wafers using a sequential integration ...
Mentor, a Siemens business, today announced that several tools in its Calibre™ nmPlatform and Analog FastSPICE (AFS™) Platform have been certified on TSMC's 5nm FinFET process technology. Mentor also ...
The 40nm gate-pitch cliff, 3D SoCs with microfluidic cooling, new fan-outs and 2.5D—it’s all on the table. An Steegen, executive vice president of semiconductor technology and systems at Imec, sat ...
January 10, 2024 -- Global Unichip Corporation (GUC), a leading global ASIC provider, has successfully taped out a complex 3D stacked die design on an advanced FinFET node process. The design, which ...
Imec has demo-ed 3D stacked FinFETs on 300mm wafers using a sequential integration approach with a 45nm fin pitch and 110nm poly pitch technology. The top layer consists of junction-less devices ...
The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node. Intel hopes to ramp up its ...
At this week's VLSI 2015 Symposium in Kyoto (Japan), imec reported new results on nanowire FETs and quantum-well FinFETs towards post-FinFET multi-gate device solutions. As the major portion of the ...
In a few weeks, Intel will release Ivy Bridge, the first mass-produced 22nm parts, and more importantly the first to use 3D "tri-gate" FinFET transistors. These CPUs will be incredibly fast and use ...
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