Imec has developed a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <350nm die-to-wafer overlay error, achieving good electrical yield. Such ...

One of the main challenges in developing semiconductor chip technology is making electronic components smaller and more effective. This difficulty is most noticeable in lithography, which is the ...

Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the ...

The Chinese module maker and the Australian National University utilized phosphorus diffusion gettering and another defect mitigation strategy to improve the quality of n-type wafers. The proposed ...